Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die.
The resolution of the printed circuit is often the limiting factor controlling interconnect density. Photo-etch and other processes for developing a printed circuit on a substrate have resolution limitations and associated cost limitations that set the level of interconnect density at a level that is less than desirable for interfacing to present integrated circuit dies that may have hundreds of external connections.
As the density of circuit traces interfacing an integrated circuit die are increased, the inter-conductor spacing must typically be decreased. However, reducing inter-conductor spacing has a disadvantage that migration and shorting may occur more frequently for lowered inter-conductor spacings, thus setting another practical limit on the interconnect density.
The above-incorporated patent applications provide improvements increasing conductor density and decreasing conductor spacings via laser-embedded circuit technologies, but are generally stand-alone rigid substrate or film substrate technologies replacing the traditional etched, printed or plated substrate technologies. Etched, printed and plated technologies provide cost advantages in that processes are well-established and volume parts can be purchased from vendors producing high volume parts using the traditional technologies.
Therefore, it would be desirable to provide a method and substrate having improved interconnect density with a low associated manufacturing cost. It would further be desirable to provide a method and substrate incorporating laser-embedded circuits, while retaining compatibility with and the advantages of etched, printed or plated substrates.